What I meant by M5 not modeling a 64 bit FPU is that M5 doesn't model a MIPS FPU with 64-bit wide FP registers. While MIPS32 processors with floating-point support have 32-bit FP registers, MIPS64 processors have 64-bit FP registers. The MIPS ISA (as defined in "MIPS32 Architecture for Programmers, Volume II: The MIPS32 Instruction Set") has support for both. And some instructions (like CEIL.L.D, CVT.PS.S, LUXC1, and many more), which look like they have some support in M5, are only relevant with a 64-bit FPU, which, as far as I can tell, M5 does not model. Or is there a way to configure M5 to model 64-bit floating point registers instead of 32-bit ones? Maybe I'm just not seeing it.
It seems that all the instructions marked "64-bit FPU Only" in the MIPS reference manual should throw some kind of warning or error if they are ever executed in M5 (if it cannot be configured to support 64-bit wide FP registers) instead of just silently doing something unpredictable. On Tue, Dec 29, 2009 at 5:27 AM, Gabe Black <[email protected]> wrote: > I notice that you comment out some function calls in this patch, and > that's probably not the right thing to do. You wouldn't be the first, > but generally it's better to either fix the problem by fixing the > function, to get rid of the broken implementation entirely (probably too > drastic), add a warning and a return at the top of the function, just > leave it for a later patch, etc. > > What do you mean about M5 not modeling a 64 bit FPU? Do you mean that it > uses native FP instructions which might be x87 based and be represented > as 80 bits? If not, supporting 64 bit FP operations shouldn't be any > different than supporting 32 bit ones or integer ops. > > Gabe > > Matt wrote: >> I followed your advice, Gabe, and fixed double-precision >> floating-point in MIPS by following the SPARC implementation. With the >> attached patch, basic double-precision stuff is fixed. There are a >> couple of things that are not yet fixed: >> 1. floating-point NaN checking. >> 2. instructions that assume a 64-bit FPU (like most of the Paired >> Single format instructions). I don't think that at this time there >> is a way to configure M5 to model a 64-bit FPU anyway. >> >> >> ------------------------------------------------------------------------ >> >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > -- Cheers, Matt _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
