I notice that you comment out some function calls in this patch, and that's probably not the right thing to do. You wouldn't be the first, but generally it's better to either fix the problem by fixing the function, to get rid of the broken implementation entirely (probably too drastic), add a warning and a return at the top of the function, just leave it for a later patch, etc.
What do you mean about M5 not modeling a 64 bit FPU? Do you mean that it uses native FP instructions which might be x87 based and be represented as 80 bits? If not, supporting 64 bit FP operations shouldn't be any different than supporting 32 bit ones or integer ops. Gabe Matt wrote: > I followed your advice, Gabe, and fixed double-precision > floating-point in MIPS by following the SPARC implementation. With the > attached patch, basic double-precision stuff is fixed. There are a > couple of things that are not yet fixed: > 1. floating-point NaN checking. > 2. instructions that assume a 64-bit FPU (like most of the Paired > Single format instructions). I don't think that at this time there > is a way to configure M5 to model a 64-bit FPU anyway. > > > ------------------------------------------------------------------------ > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
