These are the updated patches that perform timing TLB translation (instead of atomic) in base_dyn_inst.hh and then split O3 memory accesses into two reads or writes when they cross a cache line boundary. All regression tests pass without problems.
Changes from last time: * Alterations to TimingSimpleCPU folded into original patch * New const variable added to compile out split code from O3CPU if the ISA does not need it * Templating on ExecContext class to avoid virtual function calls * All calls to read / write for O3CPU now just have NULL for the split packets if the split hasn't occured (instead of using different functions) Any further comments appreciated. Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
