Hi everyone, I just realised that I didn't ever actually commit these patches. Does anyone have any problems with them, or can I go ahead? I know it's ISCA rebuttal period, so no rush (it's been a month and a half anyhow, I'm sure a little longer won't hurt!)
Cheers Tim On Mon, 14 Dec 2009 10:10:39 -0500, Timothy M. Jones <[email protected]> wrote: > These are the updated patches that perform timing TLB translation > (instead > of atomic) in base_dyn_inst.hh and then split O3 memory accesses into two > reads or writes when they cross a cache line boundary. All regression > tests > pass without problems. > > Changes from last time: > * Alterations to TimingSimpleCPU folded into original patch > * New const variable added to compile out split code from O3CPU if the > ISA does not need it > * Templating on ExecContext class to avoid virtual function calls > * All calls to read / write for O3CPU now just have NULL for the split > packets if the split hasn't occured (instead of using different > functions) > > Any further comments appreciated. > > Tim > -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
