On Thu, Dec 17, 2009 at 1:59 PM, Gabriel Michael Black <[email protected]> wrote: > > Yeah, picking the microops was a big concern for me when I was > starting out. If you remember, I closely based what we have now on > that patent I found for what looks like an older, 32 bit version of > AMD's integer microop set. The SSE microops I just made up, but I > spend a decent amount of time (a day or two) surveying the > instructions, grouping them in various ways, identifying common > behaviors, etc. In the end it's all a guess/approximation and it can > never be 100% right like has been said, but the choice was far from > arbitrary. I (and AMD before me, so to speak) did ask "if I'm going to > implement x86, what uops should I implement to be able to do that > efficiently".
I didn't mean to imply that there was any fundamental problem, or that you hadn't implemented the uops with x86 in mind (since clearly you did). I just have the vague impression, that if there's a range from 1 to 10 where 1 is "let's just use the MIPS ISA for our uops" and 10 is "let's define a new uop for each macroinstruction", we're somewhere around 5 and maybe we should be more like 6 or 7. That's all. Steve _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
