# HG changeset patch
# User Brad Beckmann <[email protected]>
# Date 1261413068 28800
# Node ID 723e67a6cf3aef261c4bc800c5d21424d2371eef
# Parent 264849268ebbd0a50e121582fb184f97bc80438e
ruby: Added Cache and MemCntrl profiler calls
diff -r 264849268ebb -r 723e67a6cf3a src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py Mon Dec 21 08:31:08 2009 -0800
+++ b/src/mem/slicc/symbols/StateMachine.py Mon Dec 21 08:31:08 2009 -0800
@@ -236,8 +236,8 @@
void set_atomic(Address addr);
void started_writes();
void clear_atomic();
- void printStats(ostream& out) const { s_profiler.dumpStats(out); }
- void clearStats() { s_profiler.clearStats(); }
+ void printStats(ostream& out) const;
+ void clearStats();
private:
''')
@@ -593,6 +593,38 @@
}
}
+void $c_ident::printStats(ostream& out) const {
+''')
+ #
+ # Cache and Memory Controllers have specific profilers associated with
+ # them. Print out these stats before dumping state transition stats.
+ #
+ for param in self.config_parameters:
+ if param.type_ast.type.ident == "CacheMemory" or \
+ param.type_ast.type.ident == "MemoryControl":
+ assert(param.pointer)
+ code(' m_${{param.ident}}_ptr->printStats(out);')
+
+ code('''
+ s_profiler.dumpStats(out);
+}
+
+void $c_ident::clearStats() {
+''')
+ #
+ # Cache and Memory Controllers have specific profilers associated with
+ # them. These stats must be cleared too.
+ #
+ for param in self.config_parameters:
+ if param.type_ast.type.ident == "CacheMemory" or \
+ param.type_ast.type.ident == "MemoryControl":
+ assert(param.pointer)
+ code(' m_${{param.ident}}_ptr->clearStats();')
+
+ code('''
+ s_profiler.clearStats();
+}
+
// Actions
''')
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