[m5-dev] [PATCH 01 of 11] ruby: Fix L1<->L2 copying in MOESI_hammer

[Brad Beckmann]

# HG changeset patch
# User Brad Beckmann <brad.beckm...@amd.com>
# Date 1261412980 28800
# Node ID 16e1f3fa0e878080a2d2e6a22d313ced2518ea24
# Parent  e1df8da6de6ac36ddcb421d7d88917c2d01d13db
ruby: Fix L1<->L2 copying in MOESI_hammer

diff -r e1df8da6de6a -r 16e1f3fa0e87 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm    Mon Dec 21 08:29:40 2009 -0800
+++ b/src/mem/protocol/MOESI_hammer-cache.sm    Mon Dec 21 08:29:40 2009 -0800
@@ -660,17 +660,21 @@
 
   action(ss_copyFromL1toL2, "\s", desc="Copy data block from L1 (I or D) to 
L2") {
     if (L1DcacheMemory.isTagPresent(address)) {
-      L2cacheMemory[address] := L1DcacheMemory[address];
+      static_cast(Entry, L2cacheMemory[address]).Dirty := static_cast(Entry, 
L1DcacheMemory[address]).Dirty;
+      static_cast(Entry, L2cacheMemory[address]).DataBlk := static_cast(Entry, 
L1DcacheMemory[address]).DataBlk;
     } else {
-      L2cacheMemory[address] := L1IcacheMemory[address];
+      static_cast(Entry, L2cacheMemory[address]).Dirty := static_cast(Entry, 
L1IcacheMemory[address]).Dirty;
+      static_cast(Entry, L2cacheMemory[address]).DataBlk := static_cast(Entry, 
L1IcacheMemory[address]).DataBlk;
     }
   }
   
   action(tt_copyFromL2toL1, "\t", desc="Copy data block from L2 to L1 (I or 
D)") {
     if (L1DcacheMemory.isTagPresent(address)) {
-      L1DcacheMemory[address] := L2cacheMemory[address];
+      static_cast(Entry, L1DcacheMemory[address]).Dirty := static_cast(Entry, 
L2cacheMemory[address]).Dirty;
+      static_cast(Entry, L1DcacheMemory[address]).DataBlk := 
static_cast(Entry, L2cacheMemory[address]).DataBlk;
     } else {
-      L1IcacheMemory[address] := L2cacheMemory[address];
+      static_cast(Entry, L1IcacheMemory[address]).Dirty := static_cast(Entry, 
L2cacheMemory[address]).Dirty;
+      static_cast(Entry, L1IcacheMemory[address]).DataBlk := 
static_cast(Entry, L2cacheMemory[address]).DataBlk;
     }
   }
 

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