Korey Sewell wrote: > The first thing I would say is that implementing this could get > interesting but definitely is doable within the current framework. > > #1 is that how do you detect a 64-bit FPU despite 32-bit INT > registers. I assume that some system register is set (cop0) so what > you need to do on the 1st hand is in the instruction format check to > see if that particular setting is enabled in the system state. If so, > then the instruction is enable to execute, if not then the instruction > is ignored/warned/or whatever the fail option is necessary. So a > similar mechanism to distinguish kernel v. user-mode instructions can > be used here. > > #2 is that if you want to recognize 64 bit operands while in MIPS32 > mode, you probably have to define a new operand type to have the > parser interpret it correctly as 64-bits instead of 32-bits. Note that > in operands.isa (?) all the types are declared .... Once you've got > the operands declared directly then it's up to the actually CPU model > to interpret your instructions correctly and do the right execution. > I'm not sure by default they would do that though so some double > checking would be needed. You shouldn't need to add any new operands to just change the width, you can use the type prefix. I think the way it's supposed to work is that all instructions in MIPS64 use the wide integer registers, and it's set up so it just works out for the 32 bit instructions. You -would- need to do something special for 64 vs. 32 bit FP registers since those might need to be combined/expanded differently. You could build that intelligence into filterDoubles.
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