Shouldn't this just be folded into the SparseMemory stuff? Also, can you use M5 stats instead of ruby stats?
Nate On Thu, Mar 18, 2010 at 2:46 PM, Brad Beckmann <[email protected]> wrote: > # HG changeset patch > # User Brad Beckmann <[email protected]> > # Date 1268941833 25200 > # Node ID e1e42f946575365817ef5cc4ea60ef65be185af2 > # Parent 35d9c8e0fb18051976659ad0d3f1fb541aee54cd > ruby: Added sparse memory stats printing > > diff --git a/src/mem/ruby/system/DirectoryMemory.cc > b/src/mem/ruby/system/DirectoryMemory.cc > --- a/src/mem/ruby/system/DirectoryMemory.cc > +++ b/src/mem/ruby/system/DirectoryMemory.cc > @@ -239,6 +239,13 @@ > > } > > +void DirectoryMemory::printStats(ostream& out) const > +{ > + if (m_use_map) { > + m_sparseMemory->printStats(out); > + } > +} > + > DirectoryMemory * > RubyDirectoryMemoryParams::create() > { > diff --git a/src/mem/ruby/system/DirectoryMemory.hh > b/src/mem/ruby/system/DirectoryMemory.hh > --- a/src/mem/ruby/system/DirectoryMemory.hh > +++ b/src/mem/ruby/system/DirectoryMemory.hh > @@ -73,6 +73,7 @@ > void invalidateBlock(PhysAddress address); > > void print(ostream& out) const; > + void printStats(ostream& out) const; > > private: > // Private Methods > diff --git a/src/mem/ruby/system/SparseMemory.cc > b/src/mem/ruby/system/SparseMemory.cc > --- a/src/mem/ruby/system/SparseMemory.cc > +++ b/src/mem/ruby/system/SparseMemory.cc > @@ -54,6 +54,15 @@ > m_number_of_bits_per_level[level] = even_level_bits; > } > m_map_head = new m5::hash_map<Address, SparseMemEntry_t>; > + > + m_total_adds = 0; > + m_total_removes = 0; > + m_adds_per_level = new uint64_t[m_number_of_levels]; > + m_removes_per_level = new uint64_t[m_number_of_levels]; > + for (int level = 0; level < m_number_of_levels; level++) { > + m_adds_per_level[level] = 0; > + m_removes_per_level[level] = 0; > + } > } > > SparseMemory::~SparseMemory() > @@ -61,6 +70,8 @@ > recursivelyRemoveTables(m_map_head, 0); > delete m_map_head; > delete [] m_number_of_bits_per_level; > + delete [] m_adds_per_level; > + delete [] m_removes_per_level; > } > > // Recursively search table hierarchy for the lowest level table. > @@ -163,6 +174,8 @@ > assert(address == line_address(address)); > assert(exist(address) == false); > > + m_total_adds++; > + > Address curAddress; > m5::hash_map<Address, SparseMemEntry_t>* curTable = m_map_head; > SparseMemEntry_t* entryStruct = NULL; > @@ -198,6 +211,7 @@ > curTable = (m5::hash_map<Address, > SparseMemEntry_t>*)(((*curTable)[curAddress]).entry); > } else { > > + m_adds_per_level[level]++; > // > // if the last level, add a directory entry. Otherwise add a map. > // > @@ -276,6 +290,7 @@ > // our table. > // > if (tableSize == 0) { > + m_removes_per_level[curInfo.level]++; > delete nextInfo.curTable; > entryStruct->entry = NULL; > curInfo.curTable->erase(curAddress); > @@ -291,6 +306,7 @@ > entryStruct->entry = NULL; > delete dirEntry; > curInfo.curTable->erase(curAddress); > + m_removes_per_level[curInfo.level]++; > //delete entryStruct; > } > return curInfo.curTable->size(); > @@ -303,6 +319,8 @@ > assert(address == line_address(address)); > assert(exist(address) != false); > > + m_total_removes++; > + > curNextInfo_t nextInfo; > > // > @@ -335,6 +353,8 @@ > assert(exist(address) != false); > assert(address == line_address(address)); > > + DEBUG_EXPR(CACHE_COMP, HighPrio, address); > + > Address curAddress; > m5::hash_map<Address, SparseMemEntry_t>* curTable = m_map_head; > Directory_Entry* entry = NULL; > @@ -356,6 +376,11 @@ > lowBit = highBit - m_number_of_bits_per_level[level]; > curAddress.setAddress(address.bitSelect(lowBit, highBit - 1)); > > + DEBUG_EXPR(CACHE_COMP, HighPrio, level); > + DEBUG_EXPR(CACHE_COMP, HighPrio, lowBit); > + DEBUG_EXPR(CACHE_COMP, HighPrio, highBit - 1); > + DEBUG_EXPR(CACHE_COMP, HighPrio, curAddress); > + > // > // Adjust the highBit value for the next level > // > @@ -380,3 +405,16 @@ > { > } > > +void SparseMemory::printStats(ostream& out) const > +{ > + out << "total_adds: " << m_total_adds << " ["; > + for (int level = 0; level < m_number_of_levels; level++) { > + out << m_adds_per_level[level] << " "; > + } > + out << "]" << endl; > + out << "total_removes: " << m_total_removes << " ["; > + for (int level = 0; level < m_number_of_levels; level++) { > + out << m_removes_per_level[level] << " "; > + } > + out << "]" << endl; > +} > diff --git a/src/mem/ruby/system/SparseMemory.hh > b/src/mem/ruby/system/SparseMemory.hh > --- a/src/mem/ruby/system/SparseMemory.hh > +++ b/src/mem/ruby/system/SparseMemory.hh > @@ -68,6 +68,8 @@ > > // Print cache contents > void print(ostream& out) const; > + void printStats(ostream& out) const; > + > private: > // Private Methods > > @@ -90,7 +92,10 @@ > int m_number_of_levels; > int* m_number_of_bits_per_level; > > - > + uint64_t m_total_adds; > + uint64_t m_total_removes; > + uint64_t* m_adds_per_level; > + uint64_t* m_removes_per_level; > }; > > // Output operator declaration > diff --git a/src/mem/slicc/symbols/StateMachine.py > b/src/mem/slicc/symbols/StateMachine.py > --- a/src/mem/slicc/symbols/StateMachine.py > +++ b/src/mem/slicc/symbols/StateMachine.py > @@ -651,6 +651,7 @@ > # > for param in self.config_parameters: > if param.type_ast.type.ident == "CacheMemory" or \ > + param.type_ast.type.ident == "DirectoryMemory" or \ > param.type_ast.type.ident == "MemoryControl": > assert(param.pointer) > code(' m_${{param.ident}}_ptr->printStats(out);') > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
