You need to use Port objects for this connection, just like the real CPUs do (and the memtester). There isn't a lot of documentation on the wiki, but I think the details are discussed in the tutorial. Using the existing CPU or memtester code as an example is probably the best route. Let us know if you have any specific questions.
Steve On Fri, May 14, 2010 at 10:16 PM, Arkaprava Basu <[email protected]> wrote: > Hi, > > We are trying to connect a dummy cpu model to caches. So we require to > connect the icache and dcache ports of this dummy cpu model to that of M5 > caches. Can anybody please tell us what is the best way to achieve this > connection ? > > Arka & Rathijit > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
