Create a Port atttribute in the associated Python object with the same
name that you match for in getPort(), then assign a pair of ports to
each other in your config file, and everything else should be
automatic.  I hope that's enough to get you looking at the right
things in the existing code, anyway.

Steve

On Sun, May 16, 2010 at 3:40 PM, Arkaprava Basu <[email protected]> wrote:
> Actually we looked into those files, especially AtomicSimpleCPU and
> Memtester, but we are getting confused on how the cache ports are getting
> connected properly. In our wrapper, we also had icacheport and dcacheport,
> but not sure from where we can register them ( i.e. get the Port::setPeer()
> called with proper parameters). We were guessing this might have been done
> through some python/swig stuff, but frankly we are getting lost somewhere.
> Any clue on this would really help us.
>
> Thank you,
> Arka & Rathijit
> Steve Reinhardt wrote:
>>
>> You need to use Port objects for this connection, just like the real
>> CPUs do (and the memtester).  There isn't a lot of documentation on
>> the wiki, but I think the details are discussed in the tutorial.
>> Using the existing CPU or memtester code as an example is probably the
>> best route.  Let us know if you have any specific questions.
>>
>> Steve
>>
>> On Fri, May 14, 2010 at 10:16 PM, Arkaprava Basu <[email protected]> wrote:
>>
>>>
>>> Hi,
>>>
>>>   We are trying to connect a dummy cpu model to caches. So we require to
>>> connect the icache and dcache ports of this dummy cpu model to that of M5
>>> caches. Can anybody please tell us what is the best way to achieve this
>>> connection ?
>>>
>>> Arka & Rathijit
>>> _______________________________________________
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>>> http://m5sim.org/mailman/listinfo/m5-dev
>>>
>>>
>>
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