On a somewhat related note, it seems like the timing simple cpu control flow has gotten pretty messy with the addition of the translation state code. To figure out what is going on you really need a large white board and a lot of time to map out the call tree and what happens on faults and the like.
Ali On Fri, 4 Jun 2010 15:14:55 -0500, Min Kyu Jeong <[email protected]> wrote: > An assertion right after the initiateAcc() has a bug - it is always > evaluated as true. > > --- a/src/cpu/simple/timing.cc > +++ b/src/cpu/simple/timing.cc > @@ -771,7 +771,9 @@ > if (_status != Running) { > // instruction will complete in dcache response callback > assert(_status == DcacheWaitResponse || > - _status == DcacheRetry || DTBWaitResponse); > + _status == DcacheRetry || > + _status == DTBWaitResponse || > + _status == IcacheWaitResponse); > > I added IcacheWaitResponse because CPU can be in that status when there is > a > fault in translation (permission, etc). It will be waiting for the first > instruction in the fault handler. > > Thanks, > > Min Kyu Jeong _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
