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Review request for Default. Summary ------- ruby: fix ruby llsc support to sync sc outcomes Added support so that ruby can determine the outcome of store conditional operations and reflect that outcome to M5 physical memory and cpus. Diffs ----- src/mem/packet.hh a75564db03c3 src/mem/protocol/RubySlicc_Exports.sm a75564db03c3 src/mem/ruby/system/CacheMemory.cc a75564db03c3 src/mem/ruby/system/RubyPort.cc a75564db03c3 src/mem/ruby/system/Sequencer.hh a75564db03c3 src/mem/ruby/system/Sequencer.cc a75564db03c3 Diff: http://reviews.m5sim.org/r/98/diff Testing ------- Thanks, Brad _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
