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src/arch/arm/isa.cc <http://reviews.m5sim.org/r/163/#comment353> I don't see why that's any better. The warns are there because I intend to implement some functionality for them at some point, but I haven't gotten around to doing it. I would both like to be reminded of this fact on access and like to get past this point at present. src/arch/arm/miscregs.hh <http://reviews.m5sim.org/r/163/#comment352> It matters because they must be moved above MISCREG_CP15_UNIMP_START to not cause a panic() when they are accessed because they're unimplemented. - Ali On 2010-08-13 09:43:07, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/163/ > ----------------------------------------------------------- > > (Updated 2010-08-13 09:43:07) > > > Review request for Default. > > > Summary > ------- > > ARM: Implement some more misc registers > > > Diffs > ----- > > src/arch/arm/isa.cc 3c48b2b3cb83 > src/arch/arm/isa/formats/misc.isa 3c48b2b3cb83 > src/arch/arm/miscregs.hh 3c48b2b3cb83 > src/arch/arm/miscregs.cc 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/163/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
