> On 2010-08-17 14:47:22, Ali Saidi wrote: > > src/arch/arm/isa.cc, line 215 > > <http://reviews.m5sim.org/r/163/diff/1/?file=1813#file1813line215> > > > > I don't see why that's any better. The warns are there because I intend > > to implement some functionality for them at some point, but I haven't > > gotten around to doing it. I would both like to be reminded of this fact on > > access and like to get past this point at present.
I think we're talking about different things. I'm talking about the ones that already return something, not the ones that are warning below that. The warning ones are fine. > On 2010-08-17 14:47:22, Ali Saidi wrote: > > src/arch/arm/miscregs.hh, line 150 > > <http://reviews.m5sim.org/r/163/diff/1/?file=1815#file1815line150> > > > > It matters because they must be moved above MISCREG_CP15_UNIMP_START to > > not cause a panic() when they are accessed because they're unimplemented. You're right, I'd forgotten about that. Never mind! - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/163/#review209 ----------------------------------------------------------- On 2010-08-13 09:43:07, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/163/ > ----------------------------------------------------------- > > (Updated 2010-08-13 09:43:07) > > > Review request for Default. > > > Summary > ------- > > ARM: Implement some more misc registers > > > Diffs > ----- > > src/arch/arm/isa.cc 3c48b2b3cb83 > src/arch/arm/isa/formats/misc.isa 3c48b2b3cb83 > src/arch/arm/miscregs.hh 3c48b2b3cb83 > src/arch/arm/miscregs.cc 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/163/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
