> On 2010-08-23 11:29:37, Gabe Black wrote: > > src/arch/arm/registers.hh, line 77 > > <http://reviews.m5sim.org/r/227/diff/1/?file=2107#file2107line77> > > > > Why was this added? I'm mostly just curious. Did something depend on > > it? I don't like the idea of constants trivially and consistently derived > > from other constants being defined in all the ISAs, but it's probably not > > worth doing anything about it here.
Alpha & MIPS have it and the inorder and ozone model requires it to be defined. I've got a assert that I haven't committed yet, and might not that verifies all registers are < TotalNumRegs. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/227/#review318 ----------------------------------------------------------- On 2010-08-23 09:36:10, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/227/ > ----------------------------------------------------------- > > (Updated 2010-08-23 09:36:10) > > > Review request for Default. > > > Summary > ------- > > ARM: fixed a bug in the arm register flattening logic (FP_Base_DepTag was set > too low) > when decoding a srs instruction, invalid mode encoding returns invalid > instruction. > this can happen when garbage instructions are fetched from mispredicted path > > > Diffs > ----- > > src/arch/arm/registers.hh 47d9409b2b7f > src/cpu/o3/rename_impl.hh 47d9409b2b7f > > Diff: http://reviews.m5sim.org/r/227/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
