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(Updated 2010-08-24 15:27:07.851020) Review request for Default. Summary ------- ARM: fixed a bug in the arm register flattening logic (FP_Base_DepTag was set too low) when decoding a srs instruction, invalid mode encoding returns invalid instruction. this can happen when garbage instructions are fetched from mispredicted path Diffs (updated) ----- src/arch/alpha/registers.hh 47d9409b2b7f src/arch/arm/registers.hh 47d9409b2b7f src/arch/mips/registers.hh 47d9409b2b7f src/arch/power/registers.hh 47d9409b2b7f src/arch/sparc/registers.hh 47d9409b2b7f src/arch/x86/registers.hh 47d9409b2b7f src/cpu/o3/rename_impl.hh 47d9409b2b7f Diff: http://reviews.m5sim.org/r/227/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
