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Review request for Default. Summary ------- ARM: Don't return the result of a table walk the same cycle it's returned. The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once. Diffs ----- src/arch/arm/table_walker.hh e78b6bba67ca src/arch/arm/table_walker.cc e78b6bba67ca Diff: http://reviews.m5sim.org/r/257/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
