changeset 7733c562e5e3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7733c562e5e3
description:
ISA: Simplify various implementations of completeAcc.
diffstat:
src/arch/alpha/isa/mem.isa | 15 +------------
src/arch/arm/isa/templates/mem.isa | 36 +++++--------------------------
src/arch/arm/isa/templates/misc.isa | 10 +-------
src/arch/mips/isa/formats/mem.isa | 37 +--------------------------------
src/arch/power/isa/formats/mem.isa | 10 +--------
src/arch/sparc/isa/formats/mem/util.isa | 9 --------
6 files changed, 11 insertions(+), 106 deletions(-)
diffs (191 lines):
diff -r fe91d5e2c374 -r 7733c562e5e3 src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Fri Oct 22 00:22:59 2010 -0700
+++ b/src/arch/alpha/isa/mem.isa Fri Oct 22 00:23:19 2010 -0700
@@ -354,20 +354,7 @@
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
+ return NoFault;
}
}};
diff -r fe91d5e2c374 -r 7733c562e5e3 src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa Fri Oct 22 00:22:59 2010 -0700
+++ b/src/arch/arm/isa/templates/mem.isa Fri Oct 22 00:23:19 2010 -0700
@@ -595,23 +595,11 @@
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
+ warn_once("Complete acc isn't called on normal stores in O3.");
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
-
- return fault;
+ return NoFault;
}
}};
@@ -621,23 +609,11 @@
PacketPtr pkt, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
+ warn_once("Complete acc isn't called on normal stores in O3.");
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
-
- return fault;
+ return NoFault;
}
}};
diff -r fe91d5e2c374 -r 7733c562e5e3 src/arch/arm/isa/templates/misc.isa
--- a/src/arch/arm/isa/templates/misc.isa Fri Oct 22 00:22:59 2010 -0700
+++ b/src/arch/arm/isa/templates/misc.isa Fri Oct 22 00:23:19 2010 -0700
@@ -387,17 +387,11 @@
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
-
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (machInst.itstateMask != 0) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
- return fault;
+ return NoFault;
}
}};
diff -r fe91d5e2c374 -r 7733c562e5e3 src/arch/mips/isa/formats/mem.isa
--- a/src/arch/mips/isa/formats/mem.isa Fri Oct 22 00:22:59 2010 -0700
+++ b/src/arch/mips/isa/formats/mem.isa Fri Oct 22 00:23:19 2010 -0700
@@ -420,42 +420,7 @@
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-
-def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
- %(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
+ return NoFault;
}
}};
diff -r fe91d5e2c374 -r 7733c562e5e3 src/arch/power/isa/formats/mem.isa
--- a/src/arch/power/isa/formats/mem.isa Fri Oct 22 00:22:59 2010 -0700
+++ b/src/arch/power/isa/formats/mem.isa Fri Oct 22 00:23:19 2010 -0700
@@ -212,15 +212,7 @@
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_dest_decl)s;
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
+ return NoFault;
}
}};
diff -r fe91d5e2c374 -r 7733c562e5e3 src/arch/sparc/isa/formats/mem/util.isa
--- a/src/arch/sparc/isa/formats/mem/util.isa Fri Oct 22 00:22:59 2010 -0700
+++ b/src/arch/sparc/isa/formats/mem/util.isa Fri Oct 22 00:23:19 2010 -0700
@@ -272,15 +272,6 @@
Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
Trace::InstRecord * traceData) const
{
- Fault fault = NoFault;
- %(op_decl)s;
-
- %(op_rd)s;
- %(postacc_code)s;
- if (fault == NoFault)
- {
- %(op_wb)s;
- }
return NoFault;
}
}};
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