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Most of these comments are pretty minor, but I think my comment for timing.cc is fairly important. It's not life or death, but there's some low hanging performance there. src/arch/alpha/isa/mem.isa <http://reviews.m5sim.org/r/256/#comment641> You might want to leave out this new blank line. src/arch/alpha/isa/mem.isa <http://reviews.m5sim.org/r/256/#comment642> And getting rid of this blank line. src/arch/alpha/isa/mem.isa <http://reviews.m5sim.org/r/256/#comment643> This doesn't need to be on its own line. src/cpu/simple/timing.cc <http://reviews.m5sim.org/r/256/#comment645> Could this be supressed in initiateAcc itself? That won't work in other models where the fault doesn't go through initiateAcc on its way back to the CPU, but it would make this check unnecessary. src/cpu/static_inst.hh <http://reviews.m5sim.org/r/256/#comment644> You could use isInstPrefetch and isDataPrefetch internally here. It's not likely to ever make a difference, but if those other functions ever get more complicated isPrefetch would pick it up automatically. It's fine if you don't, but I thought I'd suggest it. - Gabe On 2010-11-05 17:26:22, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/256/ > ----------------------------------------------------------- > > (Updated 2010-11-05 17:26:22) > > > Review request for Default. > > > Summary > ------- > > ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. > > This change modifies the way prefetches work. They are now like normal loads > that don't writeback a register. Previously prefetches were supposed to call > prefetch() on the exection context, so they executed with execute() methods > instead of initiateAcc() completeAcc(). The prefetch() methods for all the > CPUs > are blank, meaning that they get executed, but don't actually do anything. > > On Alpha dead cache copy code was removed and prefetches are now normal ops. > They count as executed operations, but still don't do anything and IsMemRef is > not longer set on them. > > On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch > instructions. The timing simple CPU doesn't try to do anything special for > prefetches now and they execute with the normal memory code path. > > > Diffs > ----- > > src/arch/alpha/isa/decoder.isa 9d60c5339ae5 > src/arch/alpha/isa/mem.isa 9d60c5339ae5 > src/arch/arm/isa/insts/ldr.isa 9d60c5339ae5 > src/arch/mips/isa/formats/mem.isa 9d60c5339ae5 > src/cpu/base_dyn_inst.hh 9d60c5339ae5 > src/cpu/base_dyn_inst_impl.hh 9d60c5339ae5 > src/cpu/checker/cpu.hh 9d60c5339ae5 > src/cpu/checker/cpu.cc 9d60c5339ae5 > src/cpu/exec_context.hh 9d60c5339ae5 > src/cpu/inorder/cpu.hh 9d60c5339ae5 > src/cpu/inorder/cpu.cc 9d60c5339ae5 > src/cpu/inorder/inorder_dyn_inst.hh 9d60c5339ae5 > src/cpu/inorder/inorder_dyn_inst.cc 9d60c5339ae5 > src/cpu/inorder/resource.hh 9d60c5339ae5 > src/cpu/inorder/resources/cache_unit.hh 9d60c5339ae5 > src/cpu/inorder/resources/cache_unit.cc 9d60c5339ae5 > src/cpu/ozone/cpu.hh 9d60c5339ae5 > src/cpu/ozone/cpu_impl.hh 9d60c5339ae5 > src/cpu/simple/base.hh 9d60c5339ae5 > src/cpu/simple/base.cc 9d60c5339ae5 > src/cpu/simple/timing.cc 9d60c5339ae5 > src/cpu/static_inst.hh 9d60c5339ae5 > > Diff: http://reviews.m5sim.org/r/256/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
