I can do that, but I think it is a bad habit that we should change. I'm happy to do it for review, but for committing it is the wrong plan because it means that there are changesets in the repo that do not pass regressions.
Ali On Nov 3, 2010, at 10:08 PM, Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/256/#review431 > ----------------------------------------------------------- > > > Please split out the code changes and the stats changes into separate > changesets (as is our habit, if not yet our official policy)... the stats > changes are just too unwieldy and make it awkward to browse the code changes. > Thanks! > > > src/arch/alpha/isa/decoder.isa > <http://reviews.m5sim.org/r/256/#comment637> > > Is there still a writeHint() method out there that just doesn't ever get > called now? Seems like if we're going to change the API to get rid of > writeHint() and prefetch() (which seems reasonable to me) we should make sure > we eliminate them thoroughly. > > > > src/cpu/simple/timing.cc > <http://reviews.m5sim.org/r/256/#comment636> > > Does swapping the order of this OR really matter? > > > - Steve > > > On 2010-11-03 16:13:11, Ali Saidi wrote: >> >> ----------------------------------------------------------- >> This is an automatically generated e-mail. To reply, visit: >> http://reviews.m5sim.org/r/256/ >> ----------------------------------------------------------- >> >> (Updated 2010-11-03 16:13:11) >> >> >> Review request for Default. >> >> >> Summary >> ------- >> >> ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. >> >> This change modifies the way prefetches work. They are now like normal loads >> that don't writeback a register. Previously prefetches were supposed to call >> prefetch() on the exection context, so they executed with execute() methods >> instead of initiateAcc() completeAcc(). The prefetch() methods for all the >> CPUs >> are blank, meaning that they get executed, but don't actually do anything. >> >> On Alpha dead cache copy code was removed and prefetches are now normal ops. >> They count as executed operations, but still don't do anything and IsMemRef >> is >> not longer set on them. >> >> On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch >> instructions. The timing simple CPU doesn't try to do anything special for >> prefetches now and they execute with the normal memory code path. >> >> >> Diffs >> ----- >> >> src/arch/alpha/isa/decoder.isa 9d60c5339ae5 >> src/arch/alpha/isa/mem.isa 9d60c5339ae5 >> src/arch/arm/isa/insts/ldr.isa 9d60c5339ae5 >> src/cpu/simple/timing.cc 9d60c5339ae5 >> src/cpu/static_inst.hh 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout 9d60c5339ae5 >> tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt 9d60c5339ae5 >> tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini >> 9d60c5339ae5 >> tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout >> 9d60c5339ae5 >> tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt >> 9d60c5339ae5 >> tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini 9d60c5339ae5 >> tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout 9d60c5339ae5 >> tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/o3-timing/simout 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/simple-timing/simout 9d60c5339ae5 >> tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout 9d60c5339ae5 >> tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout 9d60c5339ae5 >> tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout 9d60c5339ae5 >> tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout 9d60c5339ae5 >> tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt 9d60c5339ae5 >> tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini 9d60c5339ae5 >> tests/quick/00.hello/ref/alpha/linux/o3-timing/simout 9d60c5339ae5 >> tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt 9d60c5339ae5 >> tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini 9d60c5339ae5 >> tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout 9d60c5339ae5 >> tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt 9d60c5339ae5 >> >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout >> 9d60c5339ae5 >> >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt >> 9d60c5339ae5 >> >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout >> 9d60c5339ae5 >> >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout >> 9d60c5339ae5 >> tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt >> 9d60c5339ae5 >> tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr 9d60c5339ae5 >> tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout 9d60c5339ae5 >> tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt 9d60c5339ae5 >> tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr 9d60c5339ae5 >> tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout 9d60c5339ae5 >> tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt 9d60c5339ae5 >> tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr 9d60c5339ae5 >> tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout 9d60c5339ae5 >> tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt 9d60c5339ae5 >> tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr 9d60c5339ae5 >> tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout 9d60c5339ae5 >> tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt 9d60c5339ae5 >> >> tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini >> 9d60c5339ae5 >> >> tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal >> 9d60c5339ae5 >> >> tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout >> 9d60c5339ae5 >> >> tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt >> 9d60c5339ae5 >> >> tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal >> 9d60c5339ae5 >> >> Diff: http://reviews.m5sim.org/r/256/diff >> >> >> Testing >> ------- >> >> >> Thanks, >> >> Ali >> >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
