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Review request for Default. Summary ------- O3: Make all instructions that write a misc register not perform the write until commit. ARM Instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Diffs ----- src/arch/arm/isa.cc f61e079ad05e src/arch/arm/isa/insts/fp.isa f61e079ad05e src/arch/arm/isa/insts/neon.isa f61e079ad05e src/arch/arm/isa/operands.isa f61e079ad05e src/arch/arm/miscregs.hh f61e079ad05e src/cpu/o3/commit_impl.hh f61e079ad05e src/cpu/o3/dyn_inst.hh f61e079ad05e src/cpu/o3/dyn_inst_impl.hh f61e079ad05e Diff: http://reviews.m5sim.org/r/298/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
