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(Updated 2010-12-31 17:28:19.882643) Review request for Default. Changes ------- Some more changes have been made to SLICC. This necessitated changes to the protocol implementation. Summary ------- This is a review request for the patch that updates the MI cache coherence protocol to conform with the new interfaces of CacheMemory and TBETable classes, and the changes in SLICC. Diffs (updated) ----- src/mem/protocol/MI_example-cache.sm UNKNOWN src/mem/protocol/MI_example-dir.sm UNKNOWN Diff: http://reviews.m5sim.org/r/335/diff Testing ------- Tested using ruby_random_tester.py with l = 10,000,000 and n = 2. Thanks, Nilay
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