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Ship it! Though it was nice to split out the SLICC and protocol patches for reviewing, I think these should be combined into a single changeset for final commit. - Steve On 2010-12-31 17:28:19, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/335/ > ----------------------------------------------------------- > > (Updated 2010-12-31 17:28:19) > > > Review request for Default. > > > Summary > ------- > > This is a review request for the patch that updates the MI cache coherence > protocol to conform with the new > interfaces of CacheMemory and TBETable classes, and the changes in SLICC. > > > Diffs > ----- > > src/mem/protocol/MI_example-cache.sm UNKNOWN > src/mem/protocol/MI_example-dir.sm UNKNOWN > > Diff: http://reviews.m5sim.org/r/335/diff > > > Testing > ------- > > Tested using ruby_random_tester.py with l = 10,000,000 and n = 2. > > > Thanks, > > Nilay > >
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