----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/380/#review707 -----------------------------------------------------------
src/cpu/base.cc <http://reviews.m5sim.org/r/380/#comment961> Don't add this blank line arbitrarily here. src/cpu/base.cc <http://reviews.m5sim.org/r/380/#comment962> Why is "static" needed here? src/cpu/o3/cpu.cc <http://reviews.m5sim.org/r/380/#comment963> readMiscRegNoEffect is for functional accesses and shouldn't modify any stats like this. src/cpu/o3/cpu.cc <http://reviews.m5sim.org/r/380/#comment964> No stats in NoEffect. src/cpu/o3/cpu.cc <http://reviews.m5sim.org/r/380/#comment965> Why would you increment by two? src/cpu/o3/cpu.cc <http://reviews.m5sim.org/r/380/#comment966> Why? src/cpu/simple/base.hh <http://reviews.m5sim.org/r/380/#comment967> No stats in NoEffect. src/cpu/simple/base.cc <http://reviews.m5sim.org/r/380/#comment968> Why not use idleFraction instead of constant(1.0) - notIdleFraction? src/cpu/simple/base.cc <http://reviews.m5sim.org/r/380/#comment969> Why caps? I see increments and not addition. How about a less jarring "/* Power model statistics. */" src/cpu/simple/base.cc <http://reviews.m5sim.org/r/380/#comment970> Don't need caps. - Gabe On 2011-01-10 10:48:23, Brad Beckmann wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/380/ > ----------------------------------------------------------- > > (Updated 2011-01-10 10:48:23) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > mcpat: Adds McPAT performance counters > > Updated patches from Rick Strong's set that modify performance counters for > McPAT > > > Diffs > ----- > > src/cpu/BaseCPU.py 9f9e10967912 > src/cpu/base.cc 9f9e10967912 > src/cpu/o3/commit.hh 9f9e10967912 > src/cpu/o3/commit_impl.hh 9f9e10967912 > src/cpu/o3/cpu.hh 9f9e10967912 > src/cpu/o3/cpu.cc 9f9e10967912 > src/cpu/o3/iew_impl.hh 9f9e10967912 > src/cpu/o3/inst_queue.hh 9f9e10967912 > src/cpu/o3/inst_queue_impl.hh 9f9e10967912 > src/cpu/o3/rename.hh 9f9e10967912 > src/cpu/o3/rename_impl.hh 9f9e10967912 > src/cpu/o3/rob.hh 9f9e10967912 > src/cpu/o3/rob_impl.hh 9f9e10967912 > src/cpu/simple/atomic.cc 9f9e10967912 > src/cpu/simple/base.hh 9f9e10967912 > src/cpu/simple/base.cc 9f9e10967912 > src/cpu/simple/timing.cc 9f9e10967912 > src/sim/System.py 9f9e10967912 > src/sim/system.hh 9f9e10967912 > src/sim/system.cc 9f9e10967912 > > Diff: http://reviews.m5sim.org/r/380/diff > > > Testing > ------- > > > Thanks, > > Brad > >
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