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src/arch/arm/predecoder.hh <http://reviews.m5sim.org/r/570/#comment1330> That would solve the general case, but I still don't think it fixes rfe safely. If a load faults you could still end taking the fault with part of the rfe observed which would be incorrect behavior. src/cpu/o3/bpred_unit_impl.hh <http://reviews.m5sim.org/r/570/#comment1331> Yea i was, that is why I changed it, but I can verify that it wasn't some other bug - Ali On 2011-03-11 15:21:28, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/570/ > ----------------------------------------------------------- > > (Updated 2011-03-11 15:21:28) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Identify branches as conditional or unconditional and direct or > indirect. > > > Diffs > ----- > > src/arch/arm/insts/branch.hh 5138d1e453f1 > src/arch/arm/isa/insts/branch.isa 5138d1e453f1 > src/arch/arm/isa/templates/branch.isa 5138d1e453f1 > src/arch/arm/predecoder.hh 5138d1e453f1 > src/arch/arm/types.hh 5138d1e453f1 > src/cpu/o3/bpred_unit_impl.hh 5138d1e453f1 > > Diff: http://reviews.m5sim.org/r/570/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
