This seems like an annoying compiler issue. If the optimization is
unsafe, then the compiler shouldn't remove the assert.
I can't remember why Tick was signed anyway, but it probably shouldn't.
Anyway, I think the fix is to do what is done for schedule() above it
and cast when and curTick() to UTIck.
Ali
On Mon, 21 Mar 2011 12:48:51 -0400, Korey Sewell <ksew...@umich.edu>
wrote:
Sorry, I didnt give the full details here. I'm using gcc4.4.1. And
when I
compile for m5.opt/debug then I get the following errors:
"[ CXX] ALPHA_FS_MOESI_CMP_directory/sim/pseudo_inst.cc -> .o
...
cc1plus: warnings being treated as errors
build/ALPHA_FS_MOESI_CMP_directory/sim/eventq.hh: In function 'void
PseudoInst::quiesceSkip(ThreadContext*)':
build/ALPHA_FS_MOESI_CMP_directory/sim/eventq.hh:526: error: assuming
signed
overflow does not occur when assuming that (X + c) < X is always
false
"
Basically, the curTick() + 1 line in pseudo_inst.cc and the
subsequent
"assert" from eventq.hh aren't playing nice together.
On Mon, Mar 21, 2011 at 9:43 AM, Ali Saidi <sa...@eecs.umich.edu>
wrote:
What is the exact problem you're trying to solve here? Why can the
compiler complain about this? What is the error message?
Ali
Sent from my ARM powered device
On Mar 20, 2011, at 8:14 PM, "Korey Sewell" <ksew...@umich.edu>
wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/603/
> -----------------------------------------------------------
>
> Review request for Default, Ali Saidi, Gabe Black, Steve
Reinhardt, and
Nathan Binkert.
>
>
> Summary
> -------
>
> sim: use nextCycle() for quiesceSkip function
> the increment of curTick causes some compiler to complain on an
assert in
the event queue
> scheduler. Since the code is only scheduling for the next cycle it
seems
safe to go ahead
> and just use the cpu's function to trick the compiler. NOTE: this
only
comes up in opt/debug
> builds since asserts are taken out of fast
>
>
> Diffs
> -----
>
> src/sim/pseudo_inst.cc c1c6f36e118e
>
> Diff: http://reviews.m5sim.org/r/603/diff
>
>
> Testing
> -------
>
> This passed the simple-atomic, simple-timing, and o3 regressions
tests
for ARM_FS.
>
>
> Thanks,
>
> Korey
>
> _______________________________________________
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
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