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I think the updated patch addresses all of your issues Gabe. I tested it with an opt binary and one problem jumped out in x86 for 20.parser an assert: m5.opt: build/X86_SE/arch/x86/emulenv.cc:49: void X86ISA::EmulEnv::doModRM(const X86ISA::ExtMachInst&): Assertion `machInst.modRM.mod != 3' failed. It looks like the assert shouldn't be there and is hit during some miss speculation. - Ali On 2011-03-30 08:41:48, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/520/ > ----------------------------------------------------------- > > (Updated 2011-03-30 08:41:48) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Tighten memory order violation checking to 16 bytes. > > The comment in the code suggests that the checking granularity should be 16 > bytes, however in reality the shift by 8 is 256 bytes which seems much > larger than required. > > > Diffs > ----- > > src/cpu/base_dyn_inst.hh d54b7775a6b0 > src/cpu/o3/O3CPU.py d54b7775a6b0 > src/cpu/o3/lsq_unit.hh d54b7775a6b0 > src/cpu/o3/lsq_unit_impl.hh d54b7775a6b0 > > Diff: http://reviews.m5sim.org/r/520/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
