Did this ever get committed? I'm running into this bug with 20.parser. Nate
On Wed, Mar 30, 2011 at 8:46 AM, Ali Saidi <sa...@umich.edu> wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/520/ > > I think the updated patch addresses all of your issues Gabe. I tested it with > an opt binary and one problem jumped out in x86 for 20.parser an assert: > m5.opt: build/X86_SE/arch/x86/emulenv.cc:49: void > X86ISA::EmulEnv::doModRM(const X86ISA::ExtMachInst&): Assertion > `machInst.modRM.mod != 3' failed. > > It looks like the assert shouldn't be there and is hit during some miss > speculation. > > > - Ali > > On March 30th, 2011, 8:41 a.m., Ali Saidi wrote: > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > By Ali Saidi. > > *Updated 2011-03-30 08:41:48* > Description > > O3: Tighten memory order violation checking to 16 bytes. > > The comment in the code suggests that the checking granularity should be 16 > bytes, however in reality the shift by 8 is 256 bytes which seems much > larger than required. > > Diffs > > - src/cpu/base_dyn_inst.hh (d54b7775a6b0) > - src/cpu/o3/O3CPU.py (d54b7775a6b0) > - src/cpu/o3/lsq_unit.hh (d54b7775a6b0) > - src/cpu/o3/lsq_unit_impl.hh (d54b7775a6b0) > > View Diff <http://reviews.m5sim.org/r/520/diff/> > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
