> On 2011-06-09 11:17:24, Gabe Black wrote:
> > This isn't a review, just a thought on the question you're asking. If the 
> > access is speculative, is it ok to use a misspeculated pc since the 
> > instruction will be thrown out anyway?
> 
> Steve Reinhardt wrote:
>     Actually after briefly looking at the code, I wonder if we don't have a 
> bigger problem here.  I'm assuming that the ThreadContext struct reflects the 
> committed state of the machine, where we really want the state relative to 
> this in-flight instruction.  Have we just been getting lucky so far?  Seems 
> like in Alpha the TLB only uses the PC to see if it's in PAL mode or not, so 
> maybe the pipeline gets flushed when we switch in and out of PAL mode and 
> thus there's never an inconsistency there even in O3.  (Nate or Ali, can you 
> confirm this?)
>     
>     Korey, can you elaborate on the kind of errors you were running into 
> without this change?
>     
>     Technically I think perhaps the TLB should be using the ExecContext 
> interface instead of the ThreadContext, but since ExecContext isn't a real 
> object, that only works if you template the call... I wonder if we really 
> should be using something like the ProxyThreadContext (see 
> cpu/thread_context.hh) wrapped around a DynInst.  Does that make sense?
>

Steve, you're correct that entrances and exists from PAL are serialize the 
pipeline so it isn't an issue. 

The thread context is pretty much used to just read miscellaneous register. Due 
to them (rightly) not being renamed and updated at commit the tlb is getting 
non-speculative state only. Any instruction that is going to do something that 
needs to be visible to later instructions needs to be marked as serializing. In 
short, I don't think we need to change the current interface and the hwrei 
change is very broken.


- Ali


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http://reviews.m5sim.org/r/743/#review1311
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On 2011-06-08 23:34:50, Korey Sewell wrote:
> 
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/743/
> -----------------------------------------------------------
> 
> (Updated 2011-06-08 23:34:50)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> -------
> 
> inorder/dtb: make sure DTB translate correct address
> The DTB expects the correct PC in the ThreadContext
> but how if the memory accesses are speculative? Shouldn't
> we send along the requestor's PC to the translate functions?
> 
> 
> Diffs
> -----
> 
>   src/cpu/inorder/resources/cache_unit.cc 77d12d8f7971 
> 
> Diff: http://reviews.m5sim.org/r/743/diff
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Korey
> 
>

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