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src/arch/alpha/tlb.cc <http://reviews.m5sim.org/r/743/#comment1767> The Request object has a PC in it which is used by the translateInst() function. Assuming that the PC object is always set correctly in Request, then translateData() can also use the Request to get the current PC value rather than the last committed state from ThreadContext. - Korey On 2011-06-10 22:52:04, Korey Sewell wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/743/ > ----------------------------------------------------------- > > (Updated 2011-06-10 22:52:04) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > inorder/dtb: make sure DTB translate correct address > The DTB expects the correct PC in the ThreadContext > but how if the memory accesses are speculative? Shouldn't > we send along the requestor's PC to the translate functions? > > > Diffs > ----- > > src/arch/alpha/tlb.cc 77d12d8f7971 > src/cpu/inorder/resources/cache_unit.cc 77d12d8f7971 > > Diff: http://reviews.m5sim.org/r/743/diff > > > Testing > ------- > > > Thanks, > > Korey > > _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
