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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/743/
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(Updated 2011-06-10 22:52:04.462095)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
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inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?


Diffs (updated)
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  src/arch/alpha/tlb.cc 77d12d8f7971 
  src/cpu/inorder/resources/cache_unit.cc 77d12d8f7971 

Diff: http://reviews.m5sim.org/r/743/diff


Testing
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Thanks,

Korey

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