Hi, I am analyzing the memory traffic within physical.cc and the size of the accesses is always 8/32/64 bit. Shouldn't all the accesses have the size of the system's cache line size?
Why (and where) is a cache line writeback of dirty data from L2 broken down into 32/64 bit accesses that are seen in physical.cc? thanks, Heiner _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
