Hi Heiner, What workload are you running, and what configuration are you using? You're right that you should be seeing cache-block-size accesses if you have a cache in your system.
Steve On Wed, Nov 30, 2011 at 1:19 PM, Heiner Litz <[email protected]>wrote: > Hi, > > I am analyzing the memory traffic within physical.cc and the size of > the accesses is always 8/32/64 bit. Shouldn't all the accesses have > the size of the system's cache line size? > > Why (and where) is a cache line writeback of dirty data from L2 broken > down into 32/64 bit accesses that are seen in physical.cc? > > thanks, Heiner > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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