If you are using Ruby, I dont think physical.cc is used.

General information would be found here:
http://gem5.org/Coherence-Protocol-Independent_Memory_Components.

On Thu, Dec 1, 2011 at 6:48 AM, Heiner Litz <
[email protected]> wrote:

> Hi Steve,
>
> thanks for your mail. I am running blackscholes from Parsec. I found
> out that when starting the simulator with the classic memory model it
> indeed works and I receive --cacheline_size sized transactions. When I
> use ruby I receive only 32 and 64 bit write/read accesses. In both
> cases I have caches enabled (--caches --l2cache --cacheline_size=64).
>
> Could you clarify the behavior of physical.cc within the Ruby memory
> system?
>
> How does it interact with MemoryControll.cc ?
>
> In the case of Ruby, how is the latency calculated as there are
> statements within MemoryControll.cc as well as in physical.cc?
>
> thanks a lot, Heiner
>
>
> On Wed, Nov 30, 2011 at 10:43 PM, Steve Reinhardt <[email protected]>
> wrote:
> > Hi Heiner,
> > What workload are you running, and what configuration are you using?
>  You're
> > right that you should be seeing cache-block-size accesses if you have a
> > cache in your system.
> > Steve
> >
> > On Wed, Nov 30, 2011 at 1:19 PM, Heiner Litz <[email protected]>
> > wrote:
> >>
> >> Hi,
> >>
> >> I am analyzing the memory traffic within physical.cc and the size of
> >> the accesses is always 8/32/64 bit. Shouldn't all the accesses have
> >> the size of the system's cache line size?
> >>
> >> Why (and where) is a cache line writeback of dirty data from L2 broken
> >> down into 32/64 bit accesses that are seen in physical.cc?
> >>
> >> thanks, Heiner
> >> _______________________________________________
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> >
> >
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-- 
- Korey
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