On Fri, 26 Oct 2012, Mann Mann wrote:
Thanks Nilay
As you mentioned, I have gone through src/sim & mem/protocol files.
Understood how Classes & Cache is maintained but still has few questions.
It will be much helpful if get specific answers
1. If a var is shared between two processors, How data flow happens & how
to trace the same in simulation?
You will need to learn about how caches maintaining coherence. Those .sm
files implement the coherence protocol. You can use debug flags to figure
out how communication takes place between different caches.
2. How L1_TBEs is maintained ?
The question is unclear. You need to be more specific.
3. I am introducing a level of cache between L1 & L2
- For that I have to define a new cache in mem/protocol <newCache>.sm &
update L1 & L2 transitions
or is there some other way to do the same.
This is one way to go. You can also have two or more levels with in the
same .sm file.
--
Nilay
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