On Sun, 4 Nov 2012, Mann wrote:
Thnx Nilay
I may be naive, not able to understand few things
wrt my previous question & Your reply
Q1. If a var is shared between two processors, How data flow happens & how
to trace the same in simulation?
You will need to learn about how caches maintaining coherence. Those .sm
files implement the coherence protocol. You can use debug flags to figure
out how communication takes place between different caches.
I have going throgh protocol/.sm files to understand Coherency & data flow
but couldn,t figure out:
- How simulator understands that a variable is shared?
Just the way an actual processor would. I suggest that you read some text
on coherence protocols --
1. Computer Architecture: A Quantitative Approach by Hennessy and
Patterson.
2. A Primer on Memory Consistency and Cache Coherence by Sorin, Hill and
Wood.
- Can you refer Some simple multiprocessor program for simulation so that I
can observe data flow between caches.
You may use ruby random tester to see how data flows between caches.
Documentation is available on gem5.org.
--
Nilay
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