On Thu, 6 Dec 2012, Abhishek Deshpande wrote:
Hello,
I am trying to find trace for Last Level Cache or L3, as I want to find
Read and Writes Hits, Misses to LLC/L3.
Using my current argument, I am able to find trace log for L1 and L2
cache. But, though I have L3 cache sizes defined, I am not getting data for
LLC in generated trace file. I can find L1 and L2 data.
My current Command Line Argument:
./build/ALPHA_ES/gem5.opt --quiet --outdir=result
--trace-file=trace_radix.out --debug-flags=Cache configs/example/se.py
--clock=2.0GHz --cpu-type=detailed --caches --l1d_size=32kB --l1i_size=32kB
--l1d_assoc=8 --l1i_assoc=4 --l2cache --l2_size=256kB --l2_assoc=8
--l3_size=8192kB --l3_assoc=16 -c
v1-splash-alpha/splash2/codes/kernels/radix/RADIX
Can you confirm that an L3 cache is present in the simulated system?
--
Nilay
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
