Hi Abhiskek, You do not need to worry about changing any coherent protocol, just place an L3 cache in the right spot. The code you have inlined looks suspicious.
I'd say something like: system.l3cache = L3Cache(…) system.membus.master = system.l3cache.cpu_side system.l3cache.mem_side = system.physmem.port That will place the L3 in-between the memory bus and the memory controller. Good luck Andreas From: Abhishek Deshpande <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Friday, 7 December 2012 14:45 To: Nilay Vaish <[email protected]<mailto:[email protected]>>, "[email protected]<mailto:[email protected]>" <[email protected]<mailto:[email protected]>> Subject: Re: [gem5-users] Query on Generating Trace File for Last Level Caches On Fri, Dec 7, 2012 at 7:44 AM, Nilay Vaish <[email protected]<mailto:[email protected]>> wrote: On Thu, 6 Dec 2012, Abhishek Deshpande wrote: Hi, I am new to Gem5. Please let me know how to enable L3 and confirm that it is working. I am using ALPHA architecture available in gem5 without any modification and using se.py configuration file as available. Since you have not made any changes, this means that there is no L3 cache in the system. Take a look at the file configs/common/CacheConfig.py. It shows how to add the L2 cache. Adding an L3 cache should be similar. -- Nilay Thank you for reply. I have added L3cache in CacheConfig.py and connected it to ports by appending following in the code : if options.l3cache: system.cpu[i].connectAllPorts(system.tol2bus, system.membus) I also updated Caches.py defining a class for L3 and added option for l3cache in Options.py After these updates when I try to run the simulation, I am facing following error. File "<string>", line 1, in <module> File "/home/abhishek/gem5/src/python/m5/main.py", line 359, in main exec filecode in scope File "configs/example/se.py", line 212, in <module> CacheConfig.config_cache(options, system) File "/home/abhishek/gem5/configs/common/CacheConfig.py", line 75, in config_cache system.l3.cpu_side = system.tol2bus.master File "/home/abhishek/gem5/src/python/m5/SimObject.py", line 726, in __getattr__ % (self.__class__.__name__, attr) AttributeError: object 'System' has no attribute 'l3' Have I missed any necessary change ? How should I define L3 attribute in system ? Do I need to implement a three level cache communication protocol, or is there a other way round ? It will be really helpful for me. Thank you very much. -- abhishek -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
