On Tue, 8 Jan 2013, Mostafa Mahmoud Hassan wrote:
I found that the kernel gets these values in this function (exists in linux-2.6.28.4/arch/x86/kernel/cpu/common.c): void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) { unsigned int n, dummy, ebx, ecx, edx, l2size; n = c->extended_cpuid_level; if (n >= 0x80000005) { cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); c->x86_cache_size = (ecx>>24) + (edx>>24);the call to cpuid is responsible for getting edx and ecx , this call ultimatley executes asm code exists in native_cpuid function in "linux-2.6.28.4/arch/x86/include/asm/processor.h"static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { /* ecx is often an input as well as an output. */ asm("cpuid" : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (*eax), "2" (*ecx)); } but it seems that the asm code is calling cpuid again !
cpuid is an x86 instruction. Read about the info returned by cpuid and figure out how gem5 implements this instruction. That should provide answer to your original question.
-- Nilay _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
