Hi Gabriel,
This was written when the only memory model available was SimpleMemory that
models fixed latency (and now also bandwidth). If you replace this with
SimleDRAM you get a DRAM controller with tuneable timing constraints. Examples
provided include DDR3-1600 and LPDDR2-S4-1066, but if you want you can dial in
any imaginable DDR memory.
In short: Yes there is a very simple way to account for it these days.
Andreas
From: Gabriel Yessin <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Wednesday, 20 February 2013 05:58
To: gem5-users <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] DDR Inaccuracies?
I was wondering if the issues discussed here were ever addressed - from
"Accuracy evaluation of GEM5 simulator system"
"According to the results, the accuracy varies from 1.39% to 17.94% depending
on the memory traffic. In the worst scenario, mismatch has been shown to
result from overly simple model of the external DDR memory in GEM5 that does
not fairly model DRAM specifics."
"This originates from a somewhat inaccurate model of the external DDR memory
for which GEM5 models latency for each access and
an optional random spread factor, therefore abstracting actual DDR complex
access patterns."
Or is there any way to account for this mismatch?
Thank you,
Gabriel
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use it for any purpose, or store or copy the information in any
medium. Thank you.
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
