Thank you for the advice. The version I'm using was just checked out last
week so it should be fine.

With regards to your other comment- is there any issue with using detailed?
If my understanding is correct, it's just an agressive, modern OoO core and
arm_detailed is the same, with some parameters set to be closer to an ARM
Cortex-15?
On Feb 20, 2013 5:51 AM, "Andreas Hansson" <[email protected]> wrote:

>  Hi Gabriel,
>
>  It should be using the DDR3-1600 config if you have an up-to-date
> version of gem5 (see configs/common/FSConfig.py)
>
>  As a minor note, you might want to use arm_detailed as your CPU
> (depending on what it is you are trying to model).
>
>  Check the config.ini to be sure.
>
>  Andreas
>
>   From: Gabriel Yessin <[email protected]>
> Reply-To: gem5 users mailing list <[email protected]>
> Date: Wednesday, 20 February 2013 10:18
> To: gem5 users mailing list <[email protected]>
> Subject: Re: [gem5-users] DDR Inaccuracies?
>
>   Is SimpleDRAM used by default?
>
>  For example, I ran my simulations with:
>
>  ./build/ARM/gem5.fast -v --dump-config=config.ini --outdir=m5out
> configs/example/fs.py -b bbench-gb
> --kernel=/home/gyessin/dist/m5/system/binaries/vmlinux.smp.mouse.arm
> --frame-capture --checkpoint-dir=checkpoint
> --disk-image=/home/gyessin/dist/m5/system/disks/ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img
> --caches --cpu-type=detailed --l1d_size=32kB --l1i_size=32kB --l2cache
> --l2_size=2048kB --clock=0.75GHz
>
>  Everything was configured using the instructions at
> http://www.m5sim.org/Bbench-gem5 and  the basic setup/install
> instructions at http://gem5.org/Introduction.
>
>  Would this have utilized SimpleDRAM or SimpleMemory?
>
>  Thank you so much for your quick response.
>
> On Wed, Feb 20, 2013 at 3:54 AM, Andreas Hansson 
> <[email protected]>wrote:
>
>>  Hi Gabriel,
>>
>>  This was written when the only memory model available was SimpleMemory
>> that models fixed latency (and now also bandwidth). If you replace this
>> with SimleDRAM you get a DRAM controller with tuneable timing constraints.
>> Examples provided include DDR3-1600 and LPDDR2-S4-1066, but if you want you
>> can dial in any imaginable DDR memory.
>>
>>  In short: Yes there is a very simple way to account for it these days.
>>
>>  Andreas
>>
>>   From: Gabriel Yessin <[email protected]>
>> Reply-To: gem5 users mailing list <[email protected]>
>> Date: Wednesday, 20 February 2013 05:58
>> To: gem5-users <[email protected]>
>> Subject: [gem5-users] DDR Inaccuracies?
>>
>>   I was wondering if the issues discussed here were ever addressed -
>> from "Accuracy evaluation of GEM5 simulator system"
>>
>>  "According to the results, the accuracy varies from 1.39% to 17.94%
>> depending on  the memory traffic.  In the worst scenario, mismatch has been
>> shown to result from overly simple model of the external DDR memory in GEM5
>> that does not fairly model DRAM specifics."
>>
>>  "This originates from a somewhat inaccurate model of the external DDR
>> memory for which GEM5 models latency for each access and
>> an optional random spread factor, therefore abstracting actual DDR
>> complex access patterns."
>>
>>  Or is there any way to account for this mismatch?
>>
>>  Thank you,
>> Gabriel
>>
>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
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>
>
>
>  --
> Gabriel Yessin
> B.S. Biomedical Engineering, May 2011
> M.S. Computer Engineering, May 2013
> The George Washington University
> 774.238.0101
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
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