Actually a correction, code in BaseCPU::getMasterPort(const string &if_name, PortID idx) is called with the correct output. The problem happens with the slaveports defined for these MasterPorts.
I want my icache_port and my second_icache_port to have different slave ports. From: [email protected] To: [email protected] Subject: RE: [gem5-users] Slave and Master Ports in gem5 Date: Sat, 27 Apr 2013 22:40:50 +0300 You mean inside the base.cc. In there I have this: BaseMasterPort & BaseCPU::getMasterPort(const string &if_name, PortID idx) { DPRINTF(MyFlag, "BaseCPU::getMasterPort : %s\n",if_name); // Get the right port based on name. This applies to all the // subclasses of the base CPU and relies on their implementation // of getDataPort and getInstPort. In all cases there methods // return a CpuPort pointer. /*changes in code made by IGN - 18 Apr*/ if (if_name == "dcache_port") { DPRINTF(MyFlag, "IGN: getDataPort is returned"); return getDataPort(); } else if (if_name == "icache_port") return getInstPort(); else if (if_name == "second_icache_port") return getsecondInstPort(); else return MemObject::getMasterPort(if_name, idx); } Actually this code is never called, because I do not see my debug message being printed out. or in the port.cc where the problem occurs: MasterPort::sendTimingReq(PacketPtr pkt) { DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name()); assert(pkt->isRequest()); return _slavePort->recvTimingReq(pkt); } _slavePort is always the same, no matter if my first or second data port is the MasterPort. From: [email protected] To: [email protected] Date: Sat, 27 Apr 2013 20:28:33 +0100 Subject: Re: [gem5-users] Slave and Master Ports in gem5 That looks alright. Make sure the cpu also has an if-statement for "second_icache_port" in getMasterPort and that it returns a unique port. The string name on the right hand side in the Python description has no importance. Andreas From: ignacio charalabidis <[email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Saturday, 27 April 2013 20:11 To: gem5 users mailing list <[email protected]> Subject: Re: [gem5-users] Slave and Master Ports in gem5 Thanks Andrea, as far as the 1 is concerned I am doing this: icache_port = MasterPort("Instruction Port") dcache_port = MasterPort("Data Port") second_icache_port = MasterPort("Second Instruction Port") _cached_ports = ['icache_port', 'dcache_port','second_icache_port'] and then the connections seems correct to me. Is there anything else? Does the name inside the Master Port plays any role? Because for example, I haven't used Second Instruction Port anywhere else. Do I need to create a new class for example, or it is not a problem that icache_port and second_icache_port use the same? Thanks, Ignatios From: [email protected] To: [email protected] Date: Sat, 27 Apr 2013 20:02:10 +0100 Subject: Re: [gem5-users] Slave and Master Ports in gem5 I would think there are three places where things could be going wrong: 1 In the python code where the ports are being connected 2 In the getMaster/SlavePort in the cache where the name from the python code is mapped to an actual port instance 3 In the port subclass used Andreas From: ignacio charalabidis <[email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Saturday, 27 April 2013 19:50 To: "[email protected]" <[email protected]> Subject: [gem5-users] Slave and Master Ports in gem5 Hello, in my config.ini file, I am having this: icache_port=system.cpu.icache.cpu_side second_icache_port=system.secondmainCpu.icache.second_cpu_side I have made some modificiations in order to have two ports in my cpus and in my caches. But then in my code, for example when I have this: MasterPort::sendTimingReq(PacketPtr pkt) { ... DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name()); ... } I see this output: system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side which is correct. But for the second_icache_port i see this: system.mainCpu.second_icache_port: return value port name system.secondmainCpu.icache.cpu_side I think at somewhere, I should define what the slave port is going to be, but I do not know where to do that. I have checked for my secondCPU as well and the same things happen. Although it appears correctly in the config.ini file, it does not return what it supposes to return. Instead it returns the same slave port as the icache_port. Any help? Edit: For example, in the BaseCPU::takeOverFrom, in the base.cc file,If I call these: BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); BaseSlavePort &second_inst_peer_port = oldCPU->getSecondInstPort().getSlavePort(); they will return the same although: oldCPU->getInstPort() is icache_port oldCPU->getSecondInstPort() is second_icache_port They will both return system.cpu.icache.cpu_side as their slave port. regards, Ignatios -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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