Re: [gem5-users] Slave and Master Ports in gem5 vol.2

[Andreas Hansson]

Hi Ignatios,

Once again, I think the topic is pretty far beyond what I would consider "user" 
concerns, and I would argue the thread should move to the dev list.

I don't think there are any issues in the C++ code you are referring to. More 
likely something goes wrong in your Python configuration or in your 
implementation of getMasterPort for the modified object. I would suggest 
starting with a very simple Python script connecting the ports you want (avoid 
the complex fs/se and CPU config etc to ensure you actually control every step 
of what is happening). Once that is under control, set a breakpoint in your 
getMasterPort and ensure that is is actually returning the port you intend when 
called with the appropriate string.

Good luck.

Andreas

From: ignacio charalabidis <ign...@hotmail.com<mailto:ign...@hotmail.com>>
Reply-To: gem5 users mailing list 
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Sunday, 28 April 2013 19:42
To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] Slave and Master Ports in gem5 vol.2

Well, I think I have found the mistake but I do not know where it comes from.

So, inside the pyobject.cc  there is that code in the connectPorts

    // generic master/slave port connection
    BaseMasterPort& masterPort = mo1->getMasterPort(name1, i1);
    BaseSlavePort& slavePort   = mo2->getSlavePort(name2, i2);

    my_inform("!! WILL CONNECT: %s WITH %s \n",name1,name2);
    my_inform("!! MasterPort %s <-> Slaveport %s 
\n",masterPort.name(),slavePort.name());

    masterPort.bind(slavePort);

 the output is this:

debug info: !! WILL CONNECT: second_icache_port WITH second_cpu_side
debug info: !! MasterPort system.cpu.second_icache_port Slaveport 
system.secondmainCpu.icache.cpu_side

Despite is says it will connect it with second_cpu_side, it connects_it with 
cpu_side.

Any help why that might happen? Where is this function that is being called?

in the port.cc it does not take arguments, so I guess it's not that, and in the 
mem_object.cc it does not return anything.

Thanks,
Ignatios

________________________________
From: andreas.hans...@arm.com<mailto:andreas.hans...@arm.com>
To: gem5-users@gem5.org<mailto:gem5-users@gem5.org>
Date: Sat, 27 Apr 2013 20:28:33 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5

That looks alright. Make sure the cpu also has an if-statement for 
"second_icache_port" in getMasterPort and that it returns a unique port.

The string name on the right hand side in the Python description has no 
importance.

Andreas

From: ignacio charalabidis <ign...@hotmail.com<mailto:ign...@hotmail.com>>
Reply-To: gem5 users mailing list 
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Saturday, 27 April 2013 20:11
To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] Slave and Master Ports in gem5

Thanks Andrea,

as far as the 1 is concerned I am doing this:

  icache_port = MasterPort("Instruction Port")
  dcache_port = MasterPort("Data Port")
  second_icache_port = MasterPort("Second Instruction Port")
   _cached_ports = ['icache_port', 'dcache_port','second_icache_port']

and then the connections seems correct to me.

Is there anything else? Does the name inside the Master Port plays any role? 
Because for example, I haven't used Second Instruction Port anywhere else.

Do I need to create a new class for example, or it is not a problem that 
icache_port and second_icache_port use the same?

Thanks,
Ignatios
________________________________
From: andreas.hans...@arm.com<mailto:andreas.hans...@arm.com>
To: gem5-users@gem5.org<mailto:gem5-users@gem5.org>
Date: Sat, 27 Apr 2013 20:02:10 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5

I would think there are three places where things could be going wrong:

1 In the python code where the ports are being connected

2 In the getMaster/SlavePort in the cache where the name from the python code 
is mapped to an actual port instance

3 In the port subclass used

Andreas

From: ignacio charalabidis <ign...@hotmail.com<mailto:ign...@hotmail.com>>
Reply-To: gem5 users mailing list 
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Saturday, 27 April 2013 19:50
To: "gem5-users@gem5.org<mailto:gem5-users@gem5.org>" 
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: [gem5-users] Slave and Master Ports in gem5

Hello,

in my config.ini file, I am having this:

icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side

I have made some modificiations in order to have two ports in my cpus and in my 
caches.

But then in my code, for example when I have this:

MasterPort::sendTimingReq(PacketPtr pkt)
{
...
    DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
...

}

I see this output:

system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side 
which is correct.
But for the second_icache_port i see this:
system.mainCpu.second_icache_port: return value port name 
system.secondmainCpu.icache.cpu_side

I think at somewhere, I should define what the slave port is going to be,  but 
I do not know where to do that. I have checked for my secondCPU as well and the 
same things happen. Although it appears correctly in the config.ini file, it 
does not return what it supposes to return. Instead it returns the same slave 
port as the icache_port.

Any help?


Edit:

For example, in the BaseCPU::takeOverFrom, in the base.cc file,If I call these:

BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
BaseSlavePort &second_inst_peer_port = 
oldCPU->getSecondInstPort().getSlavePort();

they will return the same although:

oldCPU->getInstPort()  is icache_port
oldCPU->getSecondInstPort()  is second_icache_port

They will both return

system.cpu.icache.cpu_side as their slave port.

regards,
Ignatios

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