Hi Anju,
Well spotted.
I'm about to post a bunch of updates to the DRAM model that address the issue
you're pointing out amongst others.
I hope to have them on the review board by next week.
Andreas
From: Anju M A <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Friday, 4 October 2013 15:56
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] Need clarification on estimateLatency() of DRAM
Hello,
I have a doubt on a piece of code in esimateLatency() function in simple_dram.cc
The code snippet is like this :
if (bank.openRow == dram_pkt->row) {
rowHitFlag = true;
if (bank.freeAt < inTime) {
// CAS latency only
accLat += tCL;
bankLat += tCL;
} else {
accLat += 0;
bankLat += 0;
}
}
My confusion is on the highlighted else block.
If it is a row hit, and the bank is free at a later time compared to the inTime
of the request, then why are both bankLatency and accessLatency set to zero?
I feel the else block should have been this way :
else {
accLat += (bank.freeAt - inTime) + tCL;
bankLat += tCL;
}
Could someone please clarify this doubt?
--
Thanks & Regards,
Anju
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use it for any purpose, or store or copy the information in any
medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
