Hi everyone,

Please have a look at a more recent version in src/mem/dram_ctrl.cc. The
DRAMCtrl has seen quite a few updates over the last months and I¹d
recommend everyone to update accordingly.

If there are still bugs, then just shout (or even better code up a patch).

Andreas

On 6/13/14, 1:49 AM, "Mostafa via gem5-users" <[email protected]> wrote:

>Anju M A <msd.anju <at> gmail.com> writes:
>
>>
>>
>>
>> Hello,
>> I have a doubt on a piece of code in esimateLatency() function in
>simple_dram.cc
>> The code snippet is like this :if (bank.openRow == dram_pkt->row) {
>>             rowHitFlag = true;            if (bank.freeAt < inTime)
>{               // CAS latency only               accLat +=
>tCL;               bankLat += tCL;            } else {
>>                 accLat += 0;                bankLat += 0;            }
>>
>}
>>
>> My confusion is on the highlighted else block.
>>
>> If it is a row hit, and the bank is free at a later time compared to
>>the
>inTime of the request, then why are both bankLatency and accessLatency
>set
>to zero?
>>
>> I feel the else block should have been this way :
>>
>> else {
>>            accLat += (bank.freeAt - inTime) + tCL;
>>
>>            bankLat += tCL;}
>>
>> Could someone please clarify this doubt?
>>
>>
>>
>>
>> -- Thanks & Regards,Anju
>>
>>
>>
>>
>>
>> _______________________________________________
>> gem5-users mailing list
>> gem5-users <at> gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>Did you get an answer for your question ? I have the same doubts too.
>
>Regards
>Mostafa
>
>
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