Hi Ahmad, At that point the packet has already been passed to the next module, and the command is thus changed.
The trace should be fine. Let me know how it goes. Andreas From: Ahmad Hassan <ahmad.has...@gmail.com<mailto:ahmad.has...@gmail.com>> Reply-To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Date: Monday, 10 February 2014 17:03 To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache Hi Andreas, I didn't modify the packet. I just modified the following print statement in recvTimingReq of CommMonitor DPRINTF(CommMonitor, "Forwarded read request"); ==> DPRINTF(CommMonitor, "Forwarded read request %s", pkt->cmdString()); I am running full system x86 simulation in detailed mode. Thanks. Ahmad On 10 February 2014 16:53, Andreas Hansson <andreas.hans...@arm.com<mailto:andreas.hans...@arm.com>> wrote: Hi Ahmad, I’m not sure what print-outs you are referring to. Are you printing the trace after capture? The monitor takes special care to store the fields of the packet before forwarding it. If you have added your own print statements, then the packet is most likely changed already, explaining why you see only responses. Andreas From: Ahmad Hassan <ahmad.has...@gmail.com<mailto:ahmad.has...@gmail.com>> Reply-To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Date: Monday, 10 February 2014 15:17 To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache Hi Andreas, I successfully managed to attach CommMonitor between CPU and L1 and got the trace as per your code suggestion: cpu.L1MONITOR = CommMonitor(trace_file = “cpu.ptrc”) cpu.dcache_port = cpu.L1MONITOR.slave cpu.L1MONITOR.master = cache.cpu_side But I do not see any read and write packets. I only see pkt->cmdString of type 'ReadResp' or 'WriteResp' in commonitor. In other words, I only see the response packets from L1 to CPU but no traffic from CPU to L1. My config looks like below: [cid:ii_1441c5e34f728e1f] Any clues please? Thanks, Ahmad On 30 January 2014 23:44, Andreas Hansson <andreas.hans...@arm.com<mailto:andreas.hans...@arm.com>> wrote: Hi Aditya, The monitor is a sort of “extension cord”, so you have to modify the point where two ports are connected, e.g. cpu.dcache_port = cache.cpu_side would instead become: cpu.monitor = CommMonitor(trace_file = “cpu.ptrc”) # note that the trace is not an ASCII text file, but a binary protobuf file cpu.dcache_port = cpu.monitor.slave cpu.monitor.master = cache.cpu_side I hope that helps. Andreas From: Aditya Deshpande <adityamdeshpa...@gmail.com<mailto:adityamdeshpa...@gmail.com>> Reply-To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Date: Thursday, 30 January 2014 22:44 To: "gem5-users@gem5.org<mailto:gem5-users@gem5.org>" <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache Hi, I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace all the memory operation requests in the system. I am running in x-86 SE mode I added following lines in the /src/cpu/BaseCPU.py file system.monitor3 = CommMonitor(trace_file="CT_mon3.txt") MasterPort("Data Port") = system.monitor3.master system.monitor3.slave = dcache_port and commented the following line dcache_port = MasterPort("Data Port") The code executes but the trace file does not get generated. The CommMonitor3 also does not get recorded in config.ini. How to generate this trace? Any alternate ideas that I can try. Regards, Aditya -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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