Ahmad Hassan <ahmad.hassan <at> gmail.com> writes:
> > Hi Andreas, > Yes you are right, If 'protoc' is in the path then SCONS picks it up automatically. > > <at> Aditya: > You need to add 'from CommMonitor import *' in src/cpu/BaseCPU.py to get CommMonitor module there. If that doesn't fix your problem then please can you verify if 'build/X86/config/have_protobuf.hh' shows '#define HAVE_PROTOBUF 1' > > Best Regards, Ahmad > > > > > > > > > On 11 February 2014 16:50, Aditya Deshpande <adityamdeshpande <at> gmail.com> wrote: > > > Ahmad / Andreas, > I had installed protobuf before. Still get the error when I add CommMonitor in /src/cpu/BaseCPU.py file. Enclosed is the log for compilation and execution dump. > > > > oneloa 785% scons -j 8 build/X86_MESI_Two_Level/gem5.optscons: Reading SConscript files ...Checking for leading underscore in global variables...(cached) noChecking for C header file Python.h... (cached) yes > > > > Checking for C library pthread... (cached) yesChecking for C library dl... (cached) yesChecking for C library util... (cached) yesChecking for C library m... (cached) yesChecking for C library python2.6... (cached) yes > > > > Checking for accept(0,0,0) in C++ library None... (cached) yesChecking for zlibVersion() in C++ library z... (cached) yesChecking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf... (cached) yesChecking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) no > > > > Checking for clock_nanosleep(0,0,NULL,NULL) in C library rt... (cached) yesChecking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library None... (cached) yesChecking for C library tcmalloc... (cached) yes > > > > Checking for C header file fenv.h... (cached) yesChecking for C header file linux/kvm.h... (cached) yesChecking size of struct kvm_xsave ... (cached) yesChecking for member exclude_host in struct perf_event_attr...(cached) yes > > > > Reading SConsoptsBuilding in /nfs/div1/adeshpan/arch/gem5/build/X86_MESI_Two_LevelUsing saved variables file /nfs/div1/adeshpan/arch/gem5/build/variables/X86_MESI_Two_Levelscons: done reading SConscript files.scons: warning: Support for pre-2.7.0 Python version (2.6.6) is deprecated. If this will cause hardship, contact dev <at> scons.tigris.org.File "/usr/ucb/scons", line 192, in <module> > > > > scons: Building targets ... [SO PARAM] BaseCPU -> X86_MESI_Two_Level/params/BaseCPU.hh [ SO SWIG] BaseCPU -> X86_MESI_Two_Level/python/m5/internal/param_BaseCPU.i [EMBED PY] X86_MESI_Two_Level/cpu/BaseCPU.py -> .cc > > > > [ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseSimpleCPU_wrap.cc -> .o [ CXX] X86_MESI_Two_Level/python/m5/internal/param_TimingSimpleCPU_wrap.cc -> .o [ CXX] X86_MESI_Two_Level/python/m5/internal/param_DummyChecker_wrap.cc -> .o > > > > [ CXX] X86_MESI_Two_Level/python/m5/internal/param_CheckerCPU_wrap.cc -> .o [ CXX] X86_MESI_Two_Level/python/m5/internal/param_O3Checker_wrap.cc -> .o [ CXX] X86_MESI_Two_Level/python/m5/internal/param_AtomicSimpleCPU_wrap.cc -> .o > > > > [ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseCPU_wrap.cc -> .o [ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseKvmCPU_wrap.cc -> .o [ CXX] X86_MESI_Two_Level/python/m5/internal/param_DerivO3CPU_wrap.cc -> .o > > > > [ CXX] X86_MESI_Two_Level/python/m5/internal/param_X86KvmCPU_wrap.cc -> .oscons: `build/X86_MESI_Two_Level/gem5.opt' is up to date.scons: done building targets.oneloa 786% ./build/X86_MESI_Two_Level/gem5.opt -v -d /nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz --debug-flags=Cache,CommMonitor,CachePort,Flag1AD --stats-file=comm1stats.txt configs/example/se.py --caches --cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c tests/test-progs/hello/bin/x86/linux/hello > > > > gem5 Simulator System. http://gem5.orggem5 is copyrighted software; use the --copyright option for details.gem5 compiled Feb 11 2014 08:19:42gem5 started Feb 11 2014 08:45:13 > > > > gem5 executing on oneloa.isi.educommand line: ./build/X86_MESI_Two_Level/gem5.opt -v -d /nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz --debug-flags=Cache,CommMonitor,CachePort,Flag1AD --stats-file=comm1stats.txt configs/example/se.py --caches --cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c tests/test-progs/hello/bin/x86/linux/hello > > > > Traceback (most recent call last): File "<string>", line 1, in <module> File "/nfs/div1/adeshpan/arch/gem5/src/python/m5/main.py", line 388, in main exec filecode in scope > > > > File "configs/example/se.py", line 254, in <module> CacheConfig.config_cache(options, system) File "/nfs/div1/adeshpan/arch/gem5/configs/common/CacheConfig.py", line 93, in config_cache > > > > system.cpu[i].addPrivateSplitL1Caches(icache, dcache, PageTableWalkerCache(), PageTableWalkerCache()) File "/nfs/div1/adeshpan/arch/gem5/src/cpu/BaseCPU.py", line 274, in addPrivateSplitL1Caches self.monitor3 = CommMonitor(trace_file ="CT_mon3.ptrc") > > > > NameError: global name 'CommMonitor' is not defined > > > Anything else I can try? I tried adding the CommMonitor files in the src/cpu folder, that also doesn't seem to work. > > > > > Regards,Aditya > > > On Tue, Feb 11, 2014 at 3:36 AM, Ahmad Hassan <ahmad.hassan <at> gmail.com> wrote: > > > > Hi Aditiya, > [Putting on the list so other people can benefit too] > > It is not required to add any 'include' header in > src/cpu/BaseCPU.py. The reason you are getting this error is because scon build system hasn't compiled the CommMonitor code. You should see this as a WARNING during scon build process that protobuf iss missing. SCON checks for google protocol buffer on your system and if scon doesn't find it then 'have_protobuf' is set to '0' and CommMonitor is not included in the build repo. You have to install google protobuf then set PROTOC environment variable to the installed dir. > > > > > > > Then you need to rebuild gem5 as: > > scons -j6 build/X86/gem5.opt > > > This time scon will build all the CommMonitor classes and you won't see any errors like '"NameError: global name 'CommMonitor' is not defined"' > > > > > > Caution: I set the PROTOC environ variable in the shell but still scon doesn't pick it up. One way of getting around this is to change SConstruct and provide the protoc path as '/usr/bin/protoc' instead of reading from environment variable: > > > > > > > ('PROTOC', 'protoc tool', "/usr/bin/protoc"), > > > > > > Hope this helps. > > Best Regards, Ahmad > > > On 11 February 2014 00:20, Aditya Deshpande <adityamdeshpande <at> gmail.com> wrote: > > > > > > > Ahmad,Thanks for the info. I had tried adding in similar way. After adding these lines, I need to recompile the code. During recompilation, it gives me an error > "NameError: global name 'CommMonitor' is not defined" > Any pointers on how you got over this error. Did you add any header files in src/cpu/BaseCPU.py > > > Regards,Aditya > > > On Mon, Feb 10, 2014 at 9:21 AM, Ahmad Hassan <ahmad.hassan <at> gmail.com> wrote: > > > > > > > Hi Aditya, > Thank for the email. i added commmonitor between cpu and L1 in src/cpu/BaseCPU.py as follows > > > #self.dcache_port = dc.cpu_side > self.L1MONITOR = CommMonitor(trace_file="L1"); > > > > > > > > self.dcache_port = self.L1MONITOR.slave > self.L1MONITOR.master = dc.cpu_side > > Good luck. > > > > > > > > > > Best Regards, Ahmad > > > On 10 February 2014 17:03, Aditya Deshpande <adityamdeshpande <at> gmail.com> wrote: > > > > > > > > > > > > Ahmed, > If you want to add CommMonitor between l1 and L2 cache > In CacheConfig.py > Comment following linessystem.l2.cpu_side = system.tol2bus.master > > > > > > > > > > system.l2.mem_side = system.membus.slave > Add following linessystem.monitor2 = CommMonitor(trace_file="CT_mon2.txt")system.monitor2.slave = system.tol2bus.mastersystem.l2.cpu_side = system.monitor2.master > > > > > > > > > > system.l2.mem_side = system.membus.slave > The following lines basically changes the hierarchy from (l1-cache -> tol2bus -> L2 Cache ->membus) to (l1cache -> tol2bus -> commMonitor monitor2 -> l2cache -> membus) > > I ran into same problem of CommMonitor being not found when i try to add commMonitor between CPU and L1D-cache. > > Did you try to add any CommMonitor there? Any ideas on how to do that. > > > > > > > > > > > > > Regards,Aditya > > > On Sun, Feb 9, 2014 at 1:38 AM, Ahmad Hassan <ahmad.hassan <at> gmail.com> wrote: > > > > > > > > > > HI Aditya, > How did you attach commonitor to L2 in > config/common/CacheConfig.py. I get import errors if I try to import 'from CommMonitor import *" in CacheConfig.py > > Please can you share the syntax of attaching L2 and L1 to commmonitor. > > > > > > > > > > > > Thanks. > > > > > On 31 January 2014 21:33, Aditya Deshpande <adityamdeshpande <at> gmail.com> wrote: > > > > > > > > > > > > > > > > > Andreas, > I understand how to add CommMonitor. I was able to trace L2 cache accesses using CommMonitor. In that case, I was adding commMonitor in config/common/CacheConfig.py > > I was able to run the simulation and get the trace. The commMonitor connections also showed in config.ini file > Now given that interface between CPU and L1 cache is set in /src/cpu/BaseCPU.py In that file when I add commMonitor between cpu dcache_port and L1dcache cpu_side nothing happens. The simulation completes but I don't see a trace file for this commMonitor, nor do I see any info regarding this commMonitor in config.ini file. > > > when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt the system by running scons command before execution? > > > Regards,Aditya > > > > > > > _______________________________________________ > gem5-users mailing listgem5-users <at> gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > _______________________________________________ > gem5-users mailing list > gem5-users <at> gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users Hi, I followed this thread and add the CommMonitor between the CPU and the L1D cache and get result is -se as following: r,401136,4,57000 w,401136,4,115000 w,401132,4,118000 r,2220,4,121000 w,401128,4,136000 ...... I tried to follow the source code but get a little confused. Can any one tell me what does each column stand for? To my understanding, the first column is R/W operation. The second stands for the address, the third is how many bytes the operation is and the last is the cpu ticks of the packet. Is that right? _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
