Hi,

I am not sure I follow.

If you have a look at the wiki, you see that gem5 supports three different port 
access methods: functional, atomic, and timing. This corresponds to TLM-2.0’s 
debug, b_transport and nb_transport. Functional is used for initialisation and 
debug, and atomic/timing are mutually exclusive and used during the actual 
simulation run. Each memory object has to implement all three.

Andreas

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Date: Friday, 28 March 2014 05:42
To: gem5-users <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] A Question on recvFunctional() and recvTiming() in DRAM 
class


Hello! I'am studying the file src/mem/simple_dram.cc and confused by the 
functional and timing access.


It seems that the functional access recvFunctional() is called first during 
which a memcpy() accesses data in DRAM; then the timing one recvTiming() is 
called to calculate latency.


While each timing access is preceded by a functional access, the first hundreds 
of functional accesses at Tick 0 are not followed by timing accesses. I am 
confused by the memory access calling methods. Could anyone give me a hint on 
that?


Thanks for your assistance.

--------------------------------

Department of Microelectronics and Nanoelectronics in Tsinghua University

Class 02     Li Jiakun





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