Hi Giorgos, Am Samstag, 4. April 2015, 20:18:26 schrieb Giorgos Kopanas: > I am trying to make Gem5 work with the DVFS as explained in the > website. While running in Atomic Simple it is working as intended but > when I change the cpu type to arm_detailed the simulation crushes > during boot. The message that is shown is the following: > > gem5.opt: build/ARM/mem/cache/cache_impl.hh:633: bool > Cache<TagStore>::recvTimingReq(PacketPtr) [with TagStore = LRU; > PacketPtr = Packet*]: Assertion `!pkt->req->isUncacheable()' failed. > > Has anyone actually ever booted the DVFS enabled kernel that is > proposed in the website with arm_detailed cpu type or is it not > supported?
This should work, we certainly use detailed mode together with DVFS. There has been quite a bit of work and flux on uncacheable things lately, are you running this with the most recent (non-stable) gem5? If yes, it might also be worthwhile to get try out some of the uncacheable patches on RB (search for uncacheable there), and / or produce some additional information to get this debugged. Thanks, Stephan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
